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Content available in repository
Personal profile
Academic background
Qilong Liu received the M.Sc. degree from Delft University of Technology, the Netherlands, in 2015. From 2016 he started to pursue the Ph.D. degree in Integrated Circuits Group at Eindhoven University of Technology, Eindhoven, the Netherlands. His research interests include high-speed data converters, beamforming systems, and wireline links.
Research profile
Qilong Liu is a PhD student in Wideband Data Converters Lab, which is part of the Integrated Circuits group. He is working on PEFERCT project, where his main goal is to design wideband power-efficient continuous-time ADCs. Besides his research, Qilong is also involved as a supervisor for the master projects.
Education/Academic qualification
Electrical engineering, Master, Microelectronics, Delft University of Technology
1 Sept 2012 → 1 Mar 2015
Electrical engineering, Bachelor, Electronic since and technology, Tianjin University
1 Sept 2008 → 1 Jul 2012
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Collaborations and top research areas from the last five years
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A 7.3 mW 200 MHz-BW 4-element Passive-Beamforming Continuous-Time ΔΣ ADC with >30dB Spatial Interferer Suppression
Schalk, R., van Mourik, P., Liu, Q., Bajoria, S., Kong, W., Radulov, G. I. & Breems, L. J., 23 Oct 2024, 2024 IEEE European Solid-State Electronics Research Conference (ESSERC). Institute of Electrical and Electronics Engineers, p. 641-644 4 p. 10719548Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS
Liu, Q. (Corresponding author), Breems, L. J., Bajoria, S., Bolatkale, M., Rutten, R. & Radulov, G., 1 Dec 2022, In: IEEE Journal of Solid-State Circuits. 57, 12, p. 3781-3793 13 p.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile5 Citations (Scopus)161 Downloads (Pure) -
A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS
Liu, Q., Breems, L., Zhang, C., Bajoria, S., Bolatkale, M., Rutten, R. & Radulov, G., 17 Mar 2022, 2022 IEEE International Solid-State Circuits Conference (ISSCC 2022). Institute of Electrical and Electronics Engineers, p. 414-416 3 p. 9731789Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
10 Citations (Scopus)12 Downloads (Pure) -
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS
Zhang, C., Breems, L., Liu, Q., Radulov, G., Bolatkale, M., Bajoria, S., Rutten, R. & Van Roermund, A. H. M., 26 Oct 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Institute of Electrical and Electronics Engineers, p. 491-494 4 p. 9567777Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
5 Citations (Scopus) -
Analysis of the inter-stage signal leakage in wide BW low OSR and high DR CT MASH ΔΣM
Liu, Q., Breems, L. J., Bajoria, S., Bolatkale, M., Zhang, C. & Radulov, G. I., 28 Sept 2020, 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers, 5 p. 9180951Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
6 Citations (Scopus)2 Downloads (Pure)