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Personal profile

Research profile

Piyush Kaul is a doctoral candidate in the Microelectronics group at the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). His research interests include millimeter wave integrated circuit (MMIC) design, CMOS power amplifiers, power combiners and IC to Antenna transitions. One of his key studies is to design a high-efficiency power amplifier for communication systems. Other research interests include the study of power combining techniques, integration and packaging with antennas.

Academic background

Piyush Kaul received his B.Sc. degree in Electronics and Communication Engineering from Birla Institute of Technology, Ranchi, India, in 2012 and M.Sc. degree in Electrical Engineering from Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands in 2017. He is currently pursuing his PhD degree in the Mixed-signal microelectronics MsM-group in the department of Electrical Engineering at Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands.

Education/Academic qualification

Electrical engineering, Master, Eindhoven University of Technology

1 Sep 201529 Aug 2017

Electrical engineering, Bachelor, Birla Institute of Technology, Mesra

24 Jul 200824 May 2012

External positions

Hardware Engineer (Research and Development), Tejas Networks, Bengaluru

3 Aug 201226 Jun 2015

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Research Output 2018 2019

  • 2 Conference contribution

An E-band silicon-IC-to-waveguide contactless transition incorporating a low-loss spatial power combiner

Kaul, P., Aljarosha, A., Smolders, A. B., Baltus, P. G. M., Matters - Kammerer, M. & Maaskant, R., 16 Jan 2019, 2018 IEEE Asia-Pacific Microwave Conference, APMC. Piscataway: Institute of Electrical and Electronics Engineers (IEEE), p. 1528-1530 3 p. 8617206

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

waveguides
silicon
microstrip transmission lines
electromagnetic coupling
insertion loss

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

Kaul, P., Gao, H., He, X. & Baltus, P. G. M., 26 Apr 2018, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers (IEEE), 5 p. 8350984

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Variable frequency oscillators
Ultra-wideband (UWB)
Electric power utilization
Phase noise
Transfer functions

Student theses

An UWB, Low-power, Low-noise Quadrature VCO using a Delay Locked Loop in a 40nm CMOS Technology

Author: Kaul, P., 29 Aug 2017

Supervisor: Gao, H. (Supervisor 1) & He, X. (External person) (Supervisor 1)

Student thesis: Master