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Dive into the research topics where Mahsa Mousavi is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
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Projects
- 2 Finished
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Enable-S3 (EE-ES)
Nelson, A. T. (Project member), Goossens, K. G. W. (Project Manager), Stuijk, S. (Project member), Tavakoli Najafabadi, R. (Project member), Mousavi, M. (Project member), van der Hagen, D. (Project communication officer) & de Mol-Regels, M. (Project communication officer)
1/05/16 → 31/05/19
Project: Research direct
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ASSUME
Jóźwiak, L. (Project member), Geilen, M. C. W. (Project Manager), Jordans, R. (Project member), Corporaal, H. (Project member), Nelson, A. T. (Project member), Sánchez Martín, V. (Project member), Goossens, K. G. W. (Project member), Mousavi, M. (Project member), van Dalfsen, J. (Project member), van der Hagen, D. (Project communication officer) & de Mol-Regels, M. (Project communication officer)
1/09/15 → 31/12/18
Project: Research direct
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MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity
Mousavi, M. (Corresponding author), Pourshaghaghi, H. R., Kumar, A. & Corporaal, H., Sept 2023, In: Microprocessors and Microsystems. 101, 12 p., 104841.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile1 Citation (Scopus)38 Downloads (Pure) -
Fault Tolerant FPGAs: where to spend the effort?
Mousavi, M., De, S., Pourshaghaghi, H. R. & Corporaal, H., 1 Aug 2019, Proceedings - Euromicro Conference on Digital System Design, DSD 2019. Konofaos, N. & Kitsos, P. (eds.). Piscataway: Institute of Electrical and Electronics Engineers, p. 651-654 4 p. 8875164Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
4 Citations (Scopus)1 Downloads (Pure) -
Scatter scrubbing: a method to reduce SEU repair time in FPGA configuration memory
Mousavi, M., Pourshaghaghi, H. R., Corporaal, H. & Kumar, A., 1 Oct 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Piscataway: Institute of Electrical and Electronics Engineers, 6 p. 8875431Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
13 Citations (Scopus)1 Downloads (Pure) -
A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA
Mousavi, M., Pourshaghaghi, H. R., Tahghighi, M., Jordans, R. & Corporaal, H., 12 Oct 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Konofaos, N., Novotny, M. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers, p. 221-228 8 p. 8491821Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile14 Citations (Scopus)695 Downloads (Pure) -
Determining the necessity of fault tolerance techniques in FPGA devices for space missions
van Harten, L. D., Mousavi, M., Jordans, R. & Pourshaghaghi, H. R., 1 Nov 2018, In: Microprocessors and Microsystems. 63, p. 1-10 10 p.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile11 Citations (Scopus)416 Downloads (Pure)