Projects per year
Personal profile
Research profile
Kanishkan Vadivel is Researcher in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). His early research interest includes developing hardware architecture for energy efficient and high-performance computing, and compiler based code-generation techniques.
Kanishkan's current research includes optimal code-generation for explicit datapath architecture(CGRA) and part of MNEMOSENE project aimed to demonstrate a new computation-in-memory architecture based on resistive devices.
Quote
Designing smart and hasty machine is hard.! I take up a challenge of designing such machines with necessary tool support for usability and optimize them for energy efficiency
Academic background
Kanishkan Vadivel obtained his Master’s degree in Embedded Systems from Eindhoven University of Technology (TU/e) in 2017 and started as a researcher in Feb 2019. Kanishkan received a bachelor degree from Coimbatore Institute of Technology(India) and has 3.5years of industrial experience in Embedded systems from Tata Engineering(India) and in Arm Ltd(Cambridge, UK).
External positions
Visiting Researcher, Tampere University of Technology
Nov 2019 → …
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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SDG 7 Affordable and Clean Energy
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Dive into the research topics where Kanishkan Vadivel is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 2 Finished
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STW Zero 15-06 P5 Dependable Autonomous Mobile Computing
Goossens, K. G. W. (Project Manager), De, S. (Project member), van der Hagen, D. (Project communication officer), de Mol-Regels, M. (Project communication officer), Vadivel, K. (Project member) & de Bruin, B. (Project member)
1/01/18 → 31/12/22
Project: Research direct
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MNEMOSENE - Computation-in-memory architecture based on resistive devices
Corporaal, H. (Project Manager), Jordans, R. (Project member), Sánchez Martín, V. (Project Manager), Stuijk, S. (Project member), Banagozar, A. (Project member), Vadivel, K. (Project member), Singh, G. (Project member), van der Hagen, D. (Project communication officer) & de Mol-Regels, M. (Project communication officer)
1/01/18 → 30/06/21
Project: Research direct
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Towards efficient code generation for exposed datapath architectures
Vadivel, K., Jordans, R., Stuijk, S., Corporaal, H., Jääskeläinen, P. & Kultala, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc., p. 86-89 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile3 Link opens in a new tab Citations (Scopus)805 Downloads (Pure) -
CIM-SIM: computation in Memory SIMuIator
Banagozar, A., Wong, S., Abu Lebdeh, M., Vadivel, K., Yu, J., Hamdioui, S., Stuijk, S. & Corporaal, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc., p. 1-4 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile24 Link opens in a new tab Citations (Scopus)685 Downloads (Pure) -
Loop overhead reduction techniques for coarse grained reconfigurable architectures
Vadivel, K., Wijtvliet, M., Jordans, R. & Corporaal, H., 28 Sept 2017, DSD 2017 - 20th Euromicro Conference on Digital System Design, 30 August - 1 September 2017, Vienna, Austriavadivel wijtvliet jordfans. Novotny, M., Kubatova, H. & Skavhaug, A. (eds.). Piscataway: Institute of Electrical and Electronics Engineers, p. 14-21 8 p. 8049762Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
7 Link opens in a new tab Citations (Scopus)6 Downloads (Pure) -
Benefits of 3D-ICs in Scaled-Up Event-Based Hybrid Accelerator Architectures
De Tenbossche, S. P. (Corresponding author), Bilgic, R. (Corresponding author), Vadivel, K., Upadhyay, P., Stefanidis, L., Biswas, D. & Milojevic, D., 3 Mar 2026, 7th IEEE International Conference on Emerging Electronics, ICEE 2025. Institute of Electrical and Electronics Engineers, 4 p. 11409953Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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REBECCA: Reconfigurable heterogeneous highly parallel processing platform for safe and secure AI
Brokalakis, A. (Corresponding author), Malakonakis, P., Harteros, K., Andronikou, D., Galanomatis, I., Savvakos, C., Tang, G., Vadivel, K., van Schaik, G. J., Ioannidis, S., Georgopoulos, K., Chrysos, G., Allfjord, A., Nouripayam, M., Prieto, A., Rodrigues, J., Mavroidis, I. & Papaefstathiou, I., Jun 2026, In: Microprocessors and Microsystems. 122, 105279.Research output: Contribution to journal › Article › Academic › peer-review
Open Access
Prizes
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HiPEAC collaboration grant
Vadivel, K. (Recipient), 2019
Prize: Other › Fellowships & memberships › Scientific
Press/Media
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Studies in the Area of Neuroscience Reported from Interuniversity Microelectronics Centre (IMEC) (SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges)
7/07/23
1 item of Media coverage
Press/Media: Expert Comment
Thesis
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Energy efficient loop mapping techniques for coarse-grained reconfigurable architecture
Vadivel, K. (Author), Corporaal, H. (Supervisor 1), Jordans, R. (Supervisor 2) & van Barkel, K. (External coach), 31 Aug 2017Student thesis: Master
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