Projects per year
Personal profile
Research profile
Kanishkan Vadivel is Researcher in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). His early research interest includes developing hardware architecture for energy efficient and high-performance computing, and compiler based code-generation techniques.
Kanishkan's current research includes optimal code-generation for explicit datapath architecture(CGRA) and part of MNEMOSENE project aimed to demonstrate a new computation-in-memory architecture based on resistive devices.
Quote
Designing smart and hasty machine is hard.! I take up a challenge of designing such machines with necessary tool support for usability and optimize them for energy efficiency
Academic background
Kanishkan Vadivel obtained his Master’s degree in Embedded Sytems from Eindhoven University of Technology (TU/e) in 2017 and started as a researcher in Feb 2019. Kanishkan received a bachelor degree from Coimbatore Institute of Technology(India) and has 3.5years of industrial experience in Embedded systems from Tata Engineering(India) and in Arm Ltd(Cambridge, UK).
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
External positions
Visiting Researcher, Tampere University of Technology
Nov 2019 → …
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Collaborations and top research areas from the last five years
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Projects
- 2 Finished
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MNEMOSENE - Computation-in-memory architecture based on resistive devices
Corporaal, H., Jordans, R., Sanchez, V., Stuijk, S., Banagozar, A., Vadivel, K., Singh, G., van der Hagen, D. & de Mol-Regels, M.
1/01/18 → 30/06/21
Project: Research direct
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STW Zero 15-06 P5 Dependable Autonomous Mobile Computing
Goossens, K. G. W., De, S., van der Hagen, D., de Mol-Regels, M., Vadivel, K. & de Bruin, E.
1/01/18 → 31/12/22
Project: Research direct
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Towards efficient code generation for exposed datapath architectures
Vadivel, K., Jordans, R., Stuijk, S., Corporaal, H., Jääskeläinen, P. & Kultala, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc, p. 86-89 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile2 Citations (Scopus)545 Downloads (Pure) -
CIM-SIM: computation in Memory SIMuIator
Banagozar, A., Wong, S., Abu Lebdeh, M., Vadivel, K., Yu, J., Hamdioui, S., Stuijk, S. & Corporaal, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc, p. 1-4 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile10 Citations (Scopus)270 Downloads (Pure) -
Loop overhead reduction techniques for coarse grained reconfigurable architectures
Vadivel, K., Wijtvliet, M., Jordans, R. & Corporaal, H., 28 Sept 2017, DSD 2017 - 20th Euromicro Conference on Digital System Design, 30 August - 1 September 2017, Vienna, Austriavadivel wijtvliet jordfans. Novotny, M., Kubatova, H. & Skavhaug, A. (eds.). Piscataway: Institute of Electrical and Electronics Engineers, p. 14-21 8 p. 8049762Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
5 Citations (Scopus)6 Downloads (Pure) -
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
Vadivel, K., de Bruin, E., Jordans, R., Corporaal, H. & Jääskeläinen, P., 4 Jan 2023, 2022 25th Euromicro Conference on Digital System Design (DSD). Fabelo, H., Ortega, S. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers, p. 157-164 8 p. 9996848Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
1 Downloads (Pure) -
SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges
Tang, G., Vadivel, K., Xu, Y., Bilgic, R., Shidqi, K., Detterer, P., Traferro, S., Konijnenburg, M., Sifalakis, M., van Schaik, G-J. & Yousefzadeh, A., Jun 2023, In: Frontiers in Neuroscience. 17, 20 p., 1187252.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile
Prizes
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HiPEAC collaboration grant
Vadivel, Kanishkan (Recipient), 2019
Prize: Other › Fellowships & memberships › Scientific
Thesis
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Energy efficient loop mapping techniques for coarse-grained reconfigurable architecture
Author: Vadivel, K., 31 Aug 2017Supervisor: Corporaal, H. (Supervisor 1), Jordans, R. (Supervisor 2) & van Barkel, K. (External person) (External coach)
Student thesis: Master
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