Projects per year
Personal profile
Research profile
Kanishkan Vadivel is Researcher in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). His early research interest includes developing hardware architecture for energy efficient and high-performance computing, and compiler based code-generation techniques.
Kanishkan's current research includes optimal code-generation for explicit datapath architecture(CGRA) and part of MNEMOSENE project aimed to demonstrate a new computation-in-memory architecture based on resistive devices.
Quote
Designing smart and hasty machine is hard.! I take up a challenge of designing such machines with necessary tool support for usability and optimize them for energy efficiency
Academic background
Kanishkan Vadivel obtained his Master’s degree in Embedded Sytems from Eindhoven University of Technology (TU/e) in 2017 and started as a researcher in Feb 2019. Kanishkan received a bachelor degree from Coimbatore Institute of Technology(India) and has 3.5years of industrial experience in Embedded systems from Tata Engineering(India) and in Arm Ltd(Cambridge, UK).
External positions
Visiting Researcher, Tampere University of Technology
Nov 2019 → …Fingerprint
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Projects
- 1 Active
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MNEMOSENE - Computation-in-memory architecture based on resistive devices
Corporaal, H., Jordans, R., Sanchez, V., Sanchez, V., Stuijk, S., Banagozar, A., Vadivel, K., Singh, G., van der Hagen, D. & de Mol-Regels, M.
1/01/18 → 30/06/21
Project: Research direct
Research output
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Towards efficient code generation for exposed datapath architectures
Vadivel, K., Jordans, R., Stuijk, S., Corporaal, H., Jääskeläinen, P. & Kultala, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc, p. 86-89 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile1 Citation (Scopus)267 Downloads (Pure) -
CIM-SIM: computation in Memory SIMuIator
Banagozar, A., Wong, S., Abu Lebdeh, M., Vadivel, K., Yu, J., Hamdioui, S., Stuijk, S. & Corporaal, H., 27 May 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (ed.). New York: Association for Computing Machinery, Inc, p. 1-4 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Open AccessFile3 Citations (Scopus)71 Downloads (Pure) -
Loop overhead reduction techniques for coarse grained reconfigurable architectures
Vadivel, K., Wijtvliet, M., Jordans, R. & Corporaal, H., 28 Sep 2017, DSD 2017 - 20th Euromicro Conference on Digital System Design, 30 August - 1 September 2017, Vienna, Austriavadivel wijtvliet jordfans. Novotny, M., Kubatova, H. & Skavhaug, A. (eds.). Piscataway: Institute of Electrical and Electronics Engineers, p. 14-21 8 p. 8049762Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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PET-to-MLIR: A polyhedral front-end for MLIR
Komisarczyk, K., Chelini, L., Vadivel, K., Jordans, R. & Corporaal, H., 26 Aug 2020, Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Trost, A., Zemva, A. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers, p. 551-556 6 p. 9217876Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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System Simulation of Memristor Based Computation in Memory Platforms
BanaGozar, A., Vadivel, K., Multanen, J., Jääskeläinen, P., Stuijk, S. & Corporaal, H., 2020, Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Proceedings. Orailoglu, A., Jung, M. & Reichenbach, M. (eds.). Springer Science and Business Media Deutschland GmbH, p. 152-168 17 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12471 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Prizes
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HiPEAC collaboration grant
Vadivel, Kanishkan (Recipient), 2019
Prize: Other › Fellowships & memberships › Scientific
Student theses
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Energy efficient loop mapping techniques for coarse-grained reconfigurable architecture
Author: Vadivel, K., 31 Aug 2017Supervisor: Corporaal, H. (Supervisor 1), Jordans, R. (Supervisor 2) & van Barkel, K. (External person) (External coach)
Student thesis: Master
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