Research Output per year
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Research profile
Fingerprint Dive into the research topics where J.A. (Hans) de Hegt is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Research Output
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs
Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A. & van Roermund, A. H. M., 29 May 2017, IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, p. 547-550 4 p. 8050369Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
A Design Methodology for Wide-Band Continuous-Time MASH ΣΔ ADC Architectures
Zhang, C., Breems, L. J., Radulov, G. I., Hegt, J. A. & van Roermund, A. H. M., 22 Mar 2016.Research output: Contribution to conference › Poster › Academic
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements
Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Hegt, J. A. & van Roermund, A. H. M., 24 May 2016, IEEE International Symposium on Circuits and Systems 2016 (ISCAS), 22-25 May 2016, Montreal, Canada. Piscataway: Institute of Electrical and Electronics Engineers, p. 1486-1489Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
2
Citations
(Scopus)
2
Downloads
(Pure)
Higher-order DWA in bandpass delta-sigma modulators and its implementation
Hu, J., Hegt, J. A., van Roermund, A. H. M. & Ouzounov, S. F., 29 Jul 2016, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, p. 73-76 4 p. 7527173Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
1
Citation
(Scopus)
A background calibration technique based on limit cycles for reconfigurable sigma delta modulators
Pol, K., Ouzounov, S. F., Hegt, H. & van Roermund, A., 20 Dec 2015, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 5, 4, p. 584-597Research output: Contribution to journal › Article › Academic › peer-review
Open Access
File
1
Citation
(Scopus)
180
Downloads
(Pure)
Student theses
A 5bit 1GS/s 2.7mW time-interleaved asynchronous digital slope ADC
Author: Ding, M., 31 Aug 2011Supervisor: van Roermund, A. (Supervisor 1), Hegt, J. (Supervisor 2) & Harpe, P. (Supervisor 2)
Student thesis: Master
Analysis and design of a pixel level analog to digital converter for very large sensor arrays
Author: Pol, K., 30 Jun 2011Supervisor: Hegt, J. (Supervisor 1) & Ouzounov, S. (External coach)
Student thesis: Master
A pre-correction method for improved static linearity using parallel DACs
Author: van den Hoven, R., 30 Apr 2006Supervisor: Radulov, G. (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
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Design of a digitally pre-corrected DAC with built-in self-measurement
Author: de Meulmeester, J., 31 Aug 2005Supervisor: Harpe, P. (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
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Design of a high-speed, high-resolution pipelined AD converter
Author: Harpe, P., 29 Feb 2004Supervisor: Zanikopoulos, M. (External person) (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
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