Research Output per year
Personal profile
Research profile
Fingerprint Dive into the research topics where J.A. (Hans) de Hegt is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 7 Similar Profiles
Digital to analog conversion
Engineering & Materials Science
Calibration
Engineering & Materials Science
Sampling
Engineering & Materials Science
Modulators
Engineering & Materials Science
Networks (circuits)
Engineering & Materials Science
Pipelines
Engineering & Materials Science
Transistors
Engineering & Materials Science
Poles
Engineering & Materials Science
Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Research Output 1988 2017
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs
Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A. & van Roermund, A. H. M., 29 May 2017, IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA. Piscataway: Institute of Electrical and Electronics Engineers, p. 547-550 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Sampling
Transistors
Feedback
Bandwidth
Networks (circuits)
A Design Methodology for Wide-Band Continuous-Time MASH ΣΔ ADC Architectures
Zhang, C., Breems, L. J., Radulov, G. I., Hegt, J. A. & van Roermund, A. H. M., 22 Mar 2016Research output: Contribution to conference › Poster › Academic
Clocks
Sampling
Topology
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements
Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Hegt, J. A. & van Roermund, A. H. M., 24 May 2016, IEEE International Symposium on Circuits and Systems 2016 (ISCAS), 22-25 May 2016, Montreal, Canada. Piscataway: Institute of Electrical and Electronics Engineers, p. 1486-1489Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Poles
Calibration
FIR filters
Transistors
Higher-order DWA in bandpass delta-sigma modulators and its implementation
Hu, J., Hegt, J. A., van Roermund, A. H. M. & Ouzounov, S. F., 29 Jul 2016, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, p. 73-76 4 p. 7527173Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Modulators
Sorting
Clocks
Robust, flexible and efficient Sigma-Delta Modulation, using limit-cycle calibration and adaptive dynamic-range scaling
Pol, K. J., 13 Oct 2016, Eindhoven: Technische Universiteit Eindhoven. 163 p.Research output: Thesis › Phd Thesis 1 (Research TU/e / Graduation TU/e) › Academic
Open Access
File
Student theses
A 5bit 1GS/s 2.7mW time-interleaved asynchronous digital slope ADC
Author: Ding, M., 31 Aug 2011Supervisor: van Roermund, A. (Supervisor 1), Hegt, J. (Supervisor 2) & Harpe, P. (Supervisor 2)
Student thesis: Master
Analysis and design of a pixel level analog to digital converter for very large sensor arrays
Author: Pol, K., 30 Jun 2011Supervisor: Hegt, J. (Supervisor 1) & Ouzounov, S. (External coach)
Student thesis: Master
A pre-correction method for improved static linearity using parallel DACs
Author: van den Hoven, R., 30 Apr 2006Supervisor: Radulov, G. (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
File
Design of a digitally pre-corrected DAC with built-in self-measurement
Author: de Meulmeester, J., 31 Aug 2005Supervisor: Harpe, P. (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
File
Design of a high-speed, high-resolution pipelined AD converter
Author: Harpe, P., 29 Feb 2004Supervisor: Zanikopoulos, M. (External person) (Supervisor 1), Hegt, J. (Supervisor 2) & van Roermund, A. (Supervisor 2)
Student thesis: Master
File