• 141 Citations

Research output per year

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Personal profile

Research profile

Hailong Jiao is an Assistant Professor in the Department of Electrical Engineering at Eindhoven University of Technology (TU/e).His key research area is low-power and variations-resilient VLSI circuit and system design. He is particularly interested in error-resilient systems, approximate computing, machine learning in VLSI, ultra-low voltage circuits, and low-power robust memory circuits. Other areas of interest include emerging devices and circuit techniques, such as 3D integration, carbon electronics, and large area electronics.

The BrainWave project is a good example of how this knowledge can be practically applied. The group is working with the Signal Processing System (SPS) group at TU/e and the Donders Institute at the Radboud University Nijmegen. Jointly, they are researching and developing a wearable brainwave processing platform that enables 24/7 healthcare of epilepsy and Parkinson's Disease patients in non-hospital environments. A novel brainwave processor analyzes and interprets EEG signals that are collected non-invasively by a multi-channel sensor interface.

Academic background

Hailong Jiao received his BSc in Electronic Information Science and Technology from Shandong University, Shandong, China, in 2004 with the highest honor. He received his MSc in Microelectronics and Solid-State Electronics from the Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, in 2008. He obtained his PhD in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2012.

Hailong has worked with IMEC, Leuven, Belgium as a part-time Visiting Researcher and is an Associate Professor in the School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School. He is also Visiting Assistant Professor with the Electronic Systems group of TU/e. In addition, he is Associate Editor of Elsevier Microelectronics Journal and World Scientific Journal of Circuits, Systems, and Computers and a member of several Technical Committees (HiPEAC, MemoCiS, ACM/SIGDA and six IEEE committees). He is member of IEEE, the IEEE Circuits and Systems Society and IEEE Solid-State Circuits Society.

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Research Output

  • 141 Citations
  • 16 Conference contribution
  • 6 Article

Low power Karnaugh map approximate adder for error compensation in loop accumulations

Yang, C. & Jiao, H., 1 Jun 2019, 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 4 p. 8790952

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • Trading digital accuracy for power in an RSSI computation of a Sensor Network Transceiver

    Detterer, P., Erdin, C., Nabi, M., de Gyvez, J. P., Basten, T. & Jiao, H., 14 May 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Piscataway: Institute of Electrical and Electronics Engineers, p. 102-107 6 p. 8715146

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 1 Citation (Scopus)
    4 Downloads (Pure)

    Crosstalk-noise-aware bus coding with low-power ground-gated repeaters

    Jiao, H., Wang, R. & He, Y., 1 Feb 2018, In : International Journal of Circuit Theory and Applications. 46, 2, p. 280-289 10 p.

    Research output: Contribution to journalArticleAcademicpeer-review

    Open Access
  • 93 Downloads (Pure)

    Datawidth-aware energy-efficient multipliers: a case for going sign magnitude

    Waeijen, L., Jiao, H., Corporaal, H. & He, Y., 12 Oct 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Konofaos, N., Novotny, M. & Skavhaug, A. (eds.). Piscataway: Institute of Electrical and Electronics Engineers, p. 54-61 8 p. 8491795

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 3 Downloads (Pure)

    Embedded toggle generator to provide realistic test conditions during test of digital 2D-SoCs and 3D-SICs

    Katselas, L., Hatzopoulos, A., Jiao, H., Papameletis, C. & Marinissen, E. J., 8 May 2018, CDNLive EMEA 2018.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionProfessional


    Electronic design automation

    1/09/15 → …


    Press / Media

    3D Test: No Longer a Bottleneck!

    Erik Jan Marinissen & Hailong Jiao


    1 item of Media coverage

    Press/Media: Expert Comment

    Student theses

    Modeling static noise margin and data retention voltage of SRAM bitcells in sub-threshold region

    Author: Wang, R., 27 Oct 2016

    Supervisor: Jiao, H. (Supervisor 1) & Fan, X. (External person) (External coach)

    Student thesis: Master