Debashis Dhar, MSc

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Personal profile


I am designing a Phase-Locked Loop (PLL) based frequency synthesizer for 60 GHz FMCW radar. The single-chip radars will be used to form a phased-array radar for imaging. My research focus is to synchronize the phases of the PLL output signals from different chips.

Education/Academic qualification

Electrical engineering, Master, Korea University


Computer systems, architectures, networks, Bachelor, Bangladesh University of Engineering and Technology


External positions

Analog Design Engineer, DOESTEK Co. Ltd.



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