Content available in repository
Content available in repository
Content available in repository
I am designing a Phase-Locked Loop (PLL) based frequency synthesizer for 60 GHz FMCW radar. The single-chip radars will be used to form a phased-array radar for imaging. My research focus is to synchronize the phases of the PLL output signals from different chips.
Electrical engineering, Master, Korea University
2009 → 2011
Computer systems, architectures, networks, Bachelor, Bangladesh University of Engineering and Technology
2002 → 2007
Analog Design Engineer, DOESTEK Co. Ltd.
2011 → 2015
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review