Research Output per year
Personal profile
Quote
I am designing a Phase-Locked Loop (PLL) based frequency synthesizer for 60 GHz FMCW radar. The single-chip radars will be used to form a phased-array radar for imaging. My research focus is to synchronize the phases of the PLL output signals from different chips.
Education/Academic qualification
Electrical engineering, Master, Korea University
2009 → 2011
Computer systems, architectures, networks, Bachelor, Bangladesh University of Engineering and Technology
2002 → 2007
External positions
Analog Design Engineer, DOESTEK Co. Ltd.
2011 → 2015Fingerprint Dive into the research topics where Debashis Dhar is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Continuous wave radar
Engineering & Materials Science
Phase locked loops
Engineering & Materials Science
Phase noise
Engineering & Materials Science
low noise
Physics & Astronomy
pumps
Physics & Astronomy
bipolar transistors
Physics & Astronomy
frequency synthesizers
Physics & Astronomy
junction transistors
Physics & Astronomy
Research Output 2017 2018
- 11 Citations
- 3 Conference contribution
Analysis of the effect of PFD sampling on charge-pump PLL stability
Dhar, D., van Zeijl, P. T. M., Milosevic, D., Gao, H. & Baltus, P. G. M., 26 Apr 2018, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, Vol. 2018-May, p. 1-5 5 p. 8351180Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Phase locked loops
Pumps
Sampling
Detectors
Feedback
Modeling and analysis of the effects of PLL phase noise on FMCW radar performance
Dhar, D., Zeijl, P. T. M., Milosevic, D., Gao, H. & van Roermund, A. H. M., 30 May 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, Maryland. Piscataway: Institute of Electrical and Electronics Engineers, 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
Continuous wave radar
Phase locked loops
Phase noise
Radar
Noise analysis of a BJT-based charge pump for low-noise PLL applications
Dhar, D., van Zeijl, P. T. M., Milosevic, D., Gao, H. & Baltus, P. G. M., Sep 2017, 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE. Piscataway: Institute of Electrical and Electronics Engineers, 4 p. 8093234Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
low noise
pumps
bipolar transistors
frequency synthesizers
junction transistors