• P.O.Box 513, Department of Electrical Engineering

    5600 MB Eindhoven

    Netherlands

Organization profile

Introduction / mission

In our research on data converters we focus on the contradicting demands of high speed, high accuracy and low power consumption of analog-to-digital (AD) and digital-to-analog (DA) converters. In many of our converters, ‘smartness’ plays an important role. Smart AD and DA conversion implies on-chip intelligence, context awareness and adaptation to user and application conditions, ambient situations and actual system status. These converters are able to test themselves, measure their performance and calibrate themselves, such that their performance can be optimized for the specific situation and can be kept optimal under changing situations.

Organisational profile

Important for our research are data converters based on sigma-delta modulation (SDM). We are working on the improvement of smart SDMs by applying our new limit-cycle theory to optimally correct their loop filters, their feedback DA converters and for stability estimation. We found new incremental methods, including a new decoding technique for highly accurate DC sensing with SDMs. In parallel we do research on ultra-high-speed SDM AD converters, using novel architectures that significantly relax the design requirements for meta-stability errors, for excess loop delay and for DAC jitter.

We derive and implement very high-speed high-resolution AD converter architectures, using a novel parallel sampling technique, exploiting information about the input signal distribution function.


Furthermore we focus on very low power AD converters with world record precision, based on oversampled successive approximation, including various techniques for noise reduction and linearity enhancement. In collaboration with Holst Centre, AD converters for implantable medical applications, and flexible-speed AD converters for multi-standard radio are implemented.


To enable future multicarrier GSM applications, we do research on extremely linear mixing DA converters for large signal bandwidths and output RF frequencies of 2-4GHz and beyond.
Advanced technologies, such as FinFET are explored to draw conclusions for future designs of data converters.

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    Research Output

    A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

    Neofytou, M., Zhou, M., Bolatkale, M., Liu, Q., Zhang, C., Radulov, G., Baltus, P. & Breems, L., 26 Apr 2018, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 5 p. 8351046

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 1 Citation (Scopus)
    3 Downloads (Pure)

    A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator

    Zhou, M., Neofytou, M., Bolatkale, M., Liu, Q., Zhang, C., Cenci, P., Radulov, G., Baltus, P. & Breems, L., 26 Apr 2018, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 5 p. 8350889

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 1 Citation (Scopus)
    2 Downloads (Pure)

    Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

    Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A. & van Roermund, A. H. M., 29 May 2017, IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, p. 547-550 4 p. 8050369

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

  • 1 Downloads (Pure)