Projects per year
Introduction / mission
We research predictable embedded-systems architectures to accelerate verification of real-time performance and safety. To speed up system design we focus on conceptual simplicity and on independent design, verification, and upgrading of applications (composability). We prove our concepts with ASIC, FPGA, middleware, and full-system demonstrators.
System design is increasingly complex, as a growing number of applications are integrated in modern systems. Some of these applications have safety and real-time requirements, such as a minimum throughput or a maximum latency, but others do not, resulting in a mixed-criticality system. To reduce cost, system resources are shared between applications, making their timing behavior inter-dependent. Real-time requirements must hence be verified for all possible combinations of concurrently executing applications, which is not feasible with commonly used simulation-based techniques. CompSOC addresses this problem using two complexity-reducing concepts: composability and predictability.
Applications in a composable system are completely isolated (in terms of space, time, and energy) and cannot affect each other’s behaviours, enabling them to be independently designed, debugged, verified, deployed, and updated. Predictable systems, on the other hand, provide lower bounds on performance, allowing applications to be verified using formal performance analysis. This is essential for real-time and safety-critical systems.
CompSOC is an architecture template for predictable and composable systems, and is based on well-defined concepts, in particular:
- the use of budgets to reserve resources thus creating virtual resources
- predictable resources and arbitration to implement budgets
- composable resources and arbitration to remove any interference between applications
- scalability by decoupling resources and their arbitration
For efficiency, the following are additionally desirable: finite schedulng interval, efficient arbitration, efficient resource sharing.
These concepts combine into the concept of a Virtual Execution Platform.
CompSOC concepts have been proven in many demonstrators on FPGA, multi-FPGA, and in ASIC with applications such as multimedia, embedded control, robotics operating system (ROS2). We have performed seminal research on predictable Networks on Chip (Aethereal, Aelite), predictable DRAM controllers (Predator, DRAMPower).
More information can be found here.
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- Electrical Engineering, Cyber-Physical Systems Center Eindhoven
- Electrical Engineering, Electronic Systems - Associate Professor
- Electrical Engineering, Model-Based Design Lab
- Electrical Engineering, CompSOC Lab- Predictable & Composable Embedded Systems
Person: UHD : Associate Professor, UD : Assistant Professor19952022
1/09/20 → 30/09/24
Project: Research direct
Delay-aware Multi-layer Multi-rate Model Predictive Control for Vehicle Platooning under Message-rate Congestion ControlIbrahim, A. M. E., Goswami, D., Li, H. & Basten, A. A., 22 Apr 2022, In: IEEE Access. 10, p. 44583-44607
Research output: Contribution to journal › Article › Academic › peer-reviewOpen AccessFile2 Downloads (Pure)
Ibrahim, E., van den Dool, B., De, S., Gomony, M. D., Huisken, J. A. & Geilen, M. C. W., 1 Mar 2022, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 69, 3, p. 1210-1220 11 p.
Research output: Contribution to journal › Article › Academic › peer-review
Frigerio, A., 21 Apr 2022, Eindhoven: Eindhoven University of Technology. 217 p.
Research output: Thesis › Phd Thesis 1 (Research TU/e / Graduation TU/e)Open AccessFile
Kees G.W. Goossens (Editorial board member)2011 → 2015
Activity: Publication peer-review and editorial work types › Editorial activity › Scientific
19 Oct 2021
Student thesis: MasterFile
6 Jul 2021
Student thesis: MasterFile