Projects per year
Organisation profile
Introduction / mission
We research predictable embedded-systems architectures to accelerate verification of real-time performance and safety. To speed up system design we focus on conceptual simplicity and on independent design, verification, and upgrading of applications (composability). We prove our concepts with ASIC, FPGA, middleware, and full-system demonstrators.
Organisational profile
System design is increasingly complex, as a growing number of applications are integrated in modern systems. Some of these applications have safety and real-time requirements, such as a minimum throughput or a maximum latency, but others do not, resulting in a mixed-criticality system. To reduce cost, system resources are shared between applications, making their timing behavior inter-dependent. Real-time requirements must hence be verified for all possible combinations of concurrently executing applications, which is not feasible with commonly used simulation-based techniques. CompSOC addresses this problem using two complexity-reducing concepts: composability and predictability.
Applications in a composable system are completely isolated (in terms of space, time, and energy) and cannot affect each other’s behaviours, enabling them to be independently designed, debugged, verified, deployed, and updated. Predictable systems, on the other hand, provide lower bounds on performance, allowing applications to be verified using formal performance analysis. This is essential for real-time and safety-critical systems.
CompSOC is an architecture template for predictable and composable systems, and is based on well-defined concepts, in particular:
- the use of budgets to reserve resources thus creating virtual resources
- predictable resources and arbitration to implement budgets
- composable resources and arbitration to remove any interference between applications
- scalability by decoupling resources and their arbitration
For efficiency, the following are additionally desirable: finite schedulng interval, efficient arbitration, efficient resource sharing.
These concepts combine into the concept of a Virtual Execution Platform.
CompSOC concepts have been proven in many demonstrators on FPGA, multi-FPGA, and in ASIC with applications such as multimedia, embedded control, robotics operating system (ROS2). We have performed seminal research on predictable Networks on Chip (Aethereal, Aelite), predictable DRAM controllers (Predator, DRAMPower).
More information can be found here.
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Collaborations and top research areas from the last five years
Profiles
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Saeid Dehnavi, MSc
- Electrical Engineering, Embedded Control Systems Lab
- Electrical Engineering, CompSOC Lab- Predictable & Composable Embedded Systems
- Electrical Engineering, Electronic Systems - Doctoral Candidate
Person: Prom. : doctoral candidate (PhD), Prom. : doctoral candidate (PhD)
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Marc C.W. Geilen
- Electrical Engineering, Cyber-Physical Systems Center Eindhoven
- Electrical Engineering, Model-Based Design Lab
- Electrical Engineering, CompSOC Lab- Predictable & Composable Embedded Systems
- Electrical Engineering, Electronic Systems - Associate Professor
Person: UHD : Associate Professor, UD : Assistant Professor
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Kees G.W. Goossens
- Electrical Engineering, Electronic Systems - Full Professor
- Electrical Engineering, CompSOC Lab- Predictable & Composable Embedded Systems
- EAISI High Tech Systems - Full Professor
Person: HGL : Professor
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Scheduling Adaptive Modular Flexible Manufacturing Systems (SAM-FMS)
Basten, A. A., Geilen, M. C. W., Nasri, M., Marce i Igual, J., de Mol-Regels, M. & Farboud, P.
1/09/20 → 30/09/24
Project: Research direct
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COMP4DRONES
Goossens, K. G. W., Dehnavi, S., Goswami, D., Sanchez, V., Koedam, M. L. P. J., Nasri, M., van der Hagen, D. & de Mol-Regels, M.
1/10/19 → 31/01/23
Project: Research direct
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Arrowhead Tools
Voeten, J. P. M., Mohammadkhani, A., Geilen, M. C. W., Basten, A. A., van der Hagen, D. & de Mol-Regels, M.
1/05/19 → 31/07/22
Project: Research direct
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Decentralized Configuration of TSCH-Based IoT Networks for Distinctive QoS: A Deep Reinforcement Learning Approach
Hajizadeh, H., Nabi, M. & Goossens, K. G. W., 1 Oct 2023, In: IEEE Internet of Things Journal. 10, 19, p. 16869-16880 12 p., 10114919.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile5 Downloads (Pure) -
Dependability of Future Edge-AI Processors: Pandora's Box
Gomony, M. D., Gebregiorgis, A., Fieback, M., Geilen, M., Stuijk, S., Richter-Brockmann, J., Bishnoi, R., Andradas, L. A., Argo, S., Güneysu, T., Taouil, M., Corporaal, H. & Hamdioui, S., 12 Jul 2023, p. 1-6.Research output: Contribution to conference › Paper › Academic
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Efficient Computation of the Max-Plus Semantics of Synchronous Dataflow Graphs
Elahi, H., Geilen, M. & Basten, T., 1 Oct 2023, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42, 10, p. 3412-3425 14 p., 10025363.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile1 Downloads (Pure)
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Microprocessors and Microsystems (Journal)
Dip Goswami (Editorial board member)
2017 → …Activity: Publication peer-review and editorial work types › Editorial activity › Scientific
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ACM Transactions on Design Automation of Electronic Systems (Journal)
Kees G.W. Goossens (Editorial board member)
2011Activity: Publication peer-review and editorial work types › Editorial activity › Scientific
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Design Automation for Embedded Systems (Journal)
Kees G.W. Goossens (Editorial board member)
2011 → 2015Activity: Publication peer-review and editorial work types › Editorial activity › Scientific
Student theses
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Accuracy Configurable ISP Accelerator for an Image-based Control System
Author: Ravattu, A. K., 19 Oct 2021Supervisor: Goswami, D. (Supervisor 1) & De, S. (Supervisor 2)
Student thesis: Master
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Accurate, Verifiable and Automated Timing Analysis of Real-Time C programs
Author: Hertogs, T. P. Y., 28 Mar 2023Supervisor: Nelson, A. T. (Supervisor 1) & Koedam, M. L. P. J. (Supervisor 2)
Student thesis: Master
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A framework for generating and evaluating error correcting memory controller designs
Author: Visser, M. S., 25 Feb 2022Supervisor: Jordans, R. (Supervisor 1), Koedam, M. L. P. J. (Supervisor 2), van Berkel, C. H. (Supervisor 2) & Ravagnani, A. (Supervisor 2)
Student thesis: Master
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