Content available in repository
Content available in repository
Organisation profile
Organisation profile
CMOS scaling is approaching its physical limit and processing demands are ever increasing. To keep the energy consumption and silicon area usage within the budget, the ASIC lab focuses its research on optimizations at different levels of design stack from applications, architecture, micro-architecture, logic, circuit, device and technology.
Introduction / mission
CMOS scaling is approaching its physical limit and processing demands are ever increasing. Our aim is to design cross-stack optimizations to push the boundaries of what is physically possible.
UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. Our work contributes towards the following SDG(s):
Fingerprint
Dive into the research topics where Application Specific Integrated Circuit Lab is active. These topic labels come from the works of this organisation's members. Together they form a unique fingerprint.
Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Profiles
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Bas F.A.H.M. Ahn
- Electrical Engineering, Electronic Systems - Doctoral Candidate
- Electrical Engineering, Application Specific Integrated Circuit Lab
Person: Prom. : doctoral candidate (PhD)
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Priscilla Allwin
- Electrical Engineering, Electronic Systems - Doctoral Candidate
- Electrical Engineering, Application Specific Integrated Circuit Lab
Person: Prom. : doctoral candidate (PhD)
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Bram van Bolderik
- Electrical Engineering, Electronic Systems - Doctoral Candidate
- Electrical Engineering, Application Specific Integrated Circuit Lab
Person: Prom. : doctoral candidate (PhD)
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Hardware/Software Co-Design Optimization for Training Recurrent Neural Networks at the Edge
Zhang, Y. (Corresponding author-nrf), Yin, B., Gomony, M. D., Corporaal, H., Trinitis, C. & Corradi, F. (Corresponding author), Mar 2025, In: Journal of Low Power Electronics and Applications. 15, 1, 26 p., 15.Research output: Contribution to journal › Article › Academic › peer-review
Open AccessFile27 Downloads (Pure) -
LLRSymNet: A Low-Complex Neural Network for LLR Estimation Through Symmetry Exploitation
Allwin, P., Gomony, M. D. & Geilen, M. C. W., 11 Mar 2025, GLOBECOM 2024 - 2024 IEEE Global Communications Conference. Institute of Electrical and Electronics Engineers, p. 2377-2382 6 p. 10901172Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
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Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks
Pes, L., Luiken, R., Corradi, F. & Frenkel, C., 30 Apr 2024, arXiv.org, 5 p.Research output: Working paper › Preprint › Professional
Open AccessFile61 Downloads (Pure)
Student theses
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Analysis of a Real-Time Control System Application Deployed in a COTS MPSoC
Argyriou, M. (Author), Gomony, M. D. (Supervisor 1), 18 Apr 2024Student thesis: Master
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A Scalable Digital Architecture for Convolutional Spiking Neural Networks
Luiken, R. (Author), 3 May 2023Student thesis: Master
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A Scalable Hardware Architecture for Efficient Sequential Learning at the Edge
Zhang, Y. (Author), Gomony, M. D. (Supervisor 1), 15 May 2024Student thesis: Master
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