Research output per year
Research output per year
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Dive into the research topics where Algorithms and Logics for Verification is active. These topic labels come from the works of this organisation's members. Together they form a unique fingerprint.
Profiles
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Tim A.C. Willemse
- Mathematics and Computer Science, Formal System Analysis - Associate Professor
- Mathematics and Computer Science, Algorithms and Logics for Verification - Associate Professor
Person: UHD : Associate Professor
Research output
- 1 Article
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Correct and efficient antichain algorithms for refinement checking
Laveaux, M., Groote, J. F. & Willemse, T. A. C., 2021, In: Logical Methods in Computer Science. 17, 1, p. 8:1-8:40 40 p., 8.Research output: Contribution to journal › Article › Academic › peer-review
Open Access